Brussels / 1 & 2 February 2025

schedule

FOSDEM24
/
Feedback

Feedback

Please answer the next questions regarding you and your personal perception of the event under discussion.
If you don't want to answer a particular question, just leave it as it is.

Title: A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs
Track: EDA devroom
Time: Saturday 2016-01-30 05:00:00

Rate from 1 to 5, 5 being the highest score

This form requires JavaScript to be enabled in your browser. If you are reading this, chances are this is not the case. You may encounter issues submitting the form.

How would you rate your personal knowledge about this topic?

How important is this topic for this conference?

What is your impression of the quality of the content?

How big was the involvement/integration of the audience?

Personal comments

If you have anything particular to say about this event feel free to do so. Criticism, suggestions for improvement or other notes are very welcome.

I am a robot

I could be a robot

FOSDEM

This year

Practical information

Media and press

Social media

FOSDEM24

Brussels / 1 & 2 February 2025

This work is licensed under the Creative Commons Attribution 2.0 Belgium Licence.
To view a copy of this licence, visit http://creativecommons.org/licenses/by/2.0/be/deed.en
or send a letter to Creative Commons, 444 Castro Street, Suite 900, Mountain View, California, 94041, USA.
All content such as talks and biographies is the sole responsibility of the speaker.